Multilayer Neural Network with Synapse Based on Two Successive Memristors
Minh-Huan Vo*
Department of Electrical and Electronics Engineering, Ho Chi Minh University of Technology and Education, 01 Vo Van Ngan, Thu Duc District, Ho Chi Minh City, Vietnam
Abstract
Introduction:
Synapse based on two successive memristors builds the synaptic weights of the artificial neural network for training three-bit parity problem and five-character recognition.
Methods:
The proposed memristor synapse circuit creates positive weights in the range [0;1], and maps it to range [-1;1] to program both the positive and negative weights. The proposed scheme achieves the same accuracy rate as the conventional bridge synapse schemes which consist of four memristors.
Results and Conclusion:
However, proposed synapse circuit decreases 50% the number of memristors and 76.88% power consumption compared to the conventional bridge memristor synapse.
Keywords: Memristor, Synapse, Pattern recognition, On-chip training, Low power, CMOS.
Article Information
Article History:
Received Date: 8/10/2018
Revision Received Date: 25/11/2018
Acceptance Date: 11/12/2018
Electronic publication date: 31/12/2018
Collection year: 2018
© 2018 Minh-Huan Vo.
open-access license: This is an open access article distributed under the terms of the Creative Commons Attribution 4.0 International Public License (CC-BY 4.0), a copy of which is available at:
https://creativecommons.org/licenses/by/4.0/legalcode. This license permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited.
* Address correspondence to this author at the Department of Electrical and Electronics Engineering, Ho Chi Minh University of Technology and Education, 01 Vo Van Ngan, Thu Duc District, Ho Chi Minh City, Vietnam; Tel: 909437522; E-mail: huanvm@hcmute.edu.vn
Open Peer Review Details |
Manuscript submitted on 8-10-2018 |
Original Manuscript |
Multilayer Neural Network with Synapse Based on Two Successive Memristors |